1. Field of the Invention
This invention relates to an elementary cell effective for constructing asynchronous superconducting logic circuits handling single-flux-quantum pulses.
2. Description of the Prior Art
Today's computers ordinarily use a synchronous processor as one of their basic components, irrespective of whether they employ semiconductor logic circuits or superconducting logic circuits using Josephson devices. In "RSFQ Logic/Memory Family: A New Josephson-Junction Technology for Sub-Terahertz-Clock-Frequency Digital Systems," IEEE Trans. Appl. Superconductivity, Vol. 1, No. 1, pp. 3-28 (1991), K. K. Likharev and V. K. Semenov propose a RSFQ (rapid single-flux-quantum) circuit for constructing high-speed synchronous logic circuits using Josephson devices.
While this RSFQ circuit handles signals as single-flux-quanta (SFQ), it is also characterized by the pulse amplifier required in the actual circuit for enabling propagation of the pulse signals. The principle of the pulse amplifier 11 used in the circuit is illustrated in FIG. 5(A). Generally speaking, the Josephson device J has a hysteresis characteristic. Specifically, when a current exceeding the critical current is passed through the device, it shifts from the zero-voltage state up to that time to a voltage state, whereafter it does not return to the zero-voltage state unless the voltage applied across the device terminals falls almost completely to zero. This is known as "latching" mode operation. In a circuit using latching Josephson devices, therefore, the individual devices have to be periodically reset by use of alternating driving current (pulse current), the rise and fall timing has to be strictly controlled, and the frequency cannot be made very high. In contrast, in the pulse amplifier 11 used with this RSFQ, the Josephson device J is used as a non-latching Josephson switch 12 whose hysteresis characteristic has been deliberately nullified by, as shown in the drawing by way of example, connecting an overdamping resistor R in parallel with the Josephson device J and other such measures. In principle, the parallel resistor R and the like are not absolutely necessary if use is made of a so-called weakly coupled Josephson device, which does not have a hysteresis characteristic. In terms of device production technology, however, junction type devices and the like having hysteresis are easier to obtain with good characteristics. Generally, therefore, a device with hysteresis is used together with a parallel resistor R, as shown in the drawing.
Since the RSFQ circuit using the non-latching Josephson switch 12 can be driven by a DC power source P, it is at least freed from restriction to an AC power source. When an input pulse Qp is applied to a pulse amplifier 11 constituted by inserting a non-latching Josephson switch 12 between a DC power source P and ground, as shown in FIG. 5(A) for example, the non-latching Josephson switch 12 once shifts to a voltage state owing to superimposition of the current from the DC power source and the input pulse Qp. However, since this shift to the voltage state causes the amount of power source current flowing into the Josephson device J to decrease gradually with passage of time, the Josephson device J eventually resets itself and returns to the zero-voltage state since it has no hysteresis characteristic. As shown in FIG. 5(C), therefore, the output pulse Qp obtained at the output terminal once exhibits a large voltage (current) rise but eventually decreases gradually with lapse of time.
For achieving the desired handling of SFQ .PHI.o pulses, it is necessary for the product (L.multidot.Io) of the inductance value L of the inductors provided in the input line to and the output line from the non-latching Josephson switch 12 and the device critical current value Io to be no greater than 0.5 .PHI.o. The value of the inductance L of the inductors can, however, be set with relative freedom within this range. Actually, it is not so common to add inductance because the inductance L of the signal propagation lines generally suffices. The point remains, however, that positive, intentional adjustment of the inductance value L can be used to regulate the pulse width, pulse sharpness and other parameters affecting the pulse waveform as well as to regulate the amplification factor (magnitude of the critical current) of the individual stages when multiple pulse amplifier 11 of this type are cascaded. It should be noted that this possibility also applies regarding the various inductances indicated in the drawings of the embodiments of the invention to be described hereinafter.
FIG. 5(B) shows a buffer amplifier 13 obtained by modifying the pulse amplifier 11 of FIG. 5(A) so as to prevent operating errors owing to reverse signal flow from the output side toward the input side. A pair of non-latching Josephson switches 12, 12 are connected in series between the power source P and ground such that, with respect to a pulse Qp applied to the input, the non-latching Josephson switch 12 provided on the upper side in the drawing does not switch because the direction of current application is reverse between the power source and the input pulse and only the lower non-latching Josephson switch 12 shifts to the voltage state, whereby power source current is diverted to the output terminal side to provide an amplified output pulse Qp such as shown in FIG. 5(C). On the other hand, if a pulse signal should be erroneously input from the output terminal side, the superimposition of the input signal and the power source current shifts the upper non-latching Josephson switch 12 to the voltage state for a given period since it is fabricated to have a smaller critical current value than the lower non-latching Josephson switch 12. As a result, the signal is prevented from flowing in reverse and does not affect the input side.
As shown in FIG. 5(D), however, when the pulse Qp propagating through the lines of the logic circuit with its signal level attenuation reduced by the pulse amplifier 11 or the buffer amplifier 13 is observed from the viewpoint of an arbitrary circuit element 14 to which it is propagated, the current value or voltage value at the input of the circuit element is zero both before and after the pulse Qp arrives, so that no distinction is possible without some modification. In the prior-art RSFQ, therefore, a circuit element 14 which has to recognize signal arrival is supplied with a timing signal T of period t so that, as shown in FIG. 5(E), the presence of the input pulse Qp is recognized at the end of the period t and an output pulse Qpo is produced only if the pulse Qp arrives within the period t. (While the circuit element 14 is shown as having a single input in the drawing, this is only for simplifying the explanation and it is possible for it to be a flip-flop circuit or an arithmetic logic circuit incorporating a flip-flop circuit.)
Thus while the prior-art RSFQ circuit discussed in the foregoing does not need an AC power source, it requires a timing signal T, namely, a clock signal in the case of constructing a logic system, and, therefore, it goes without saying that the system is limited to the synchronous type. While it is true, as pointed out at the beginning of this specification, that among the various synchronous systems, the system constructed according to the configuration principle of the RSFQ circuit which handles SFQ pulses as logic signals has many superior aspects, the fact that it is a synchronous system means that, as with other synchronous systems, the basic performance, particularly the upper limit of the operating speed, is restricted by the clock frequency.
The remarkable advances made in Josephson device technology in recent years can be seen, for example, from ultra-high speed devices with switching delay times of only several picoseconds that have been achieved in the laboratory. In a synchronous system constructed on a chip with an area typical of current integrated circuits (10 mm.times.10 mm), however, the system performance saturates when the device operating delay time reaches a maximum of several tens of picoseconds. This is because the signal propagation delay time of the wiring makes it impossible to distribute a clock signal matched to the device speed. Thus, even though LSIs using devices which themselves have operating speeds on this order have actually been realized, they are unable to fully utilize the ultra-speed operating capability of the Josephson devices they include. Although devices with operating speeds of one picosecond are expected before the end of the century, the extent to which the ultra-high speed of these devices can be reflected in system performance is clearly limited in the case of synchronous systems. In fact, synchronous systems are currently very near reaching their limit in this respect, if they haven't reached it already.
One solution to this problem is to use the asynchronous system configuration which operates without a clock based solely on the causality of event occurrence. The performance of an asynchronous processor is determined not by the "maximum value" but by the "average value" of the processing and the delay. Since it is unaffected by unpredictable timing changes and the like, the high-speed capability of the device can be directly reflected in the system performance, so that the power of the system increases with increasing device operating speed.
However, it is not possible to apply the configuration principle of the synchronous logic circuits in the RSFQ circuit discussed in the foregoing to an asynchronous system without modification. A circuit element which, like the basic pulse amplifier 11 shown in FIG. 5(A) or the buffer amplifier 13 shown in FIG. 5(B), for example, responds to mere application of a signal pulse Qp by simply amplifying its voltage or current level, can be used substantially as it is in an asynchronous system because there is no need to consider the presence of a timing signal. (It is for this reason that the pulse amplifier 11 and buffer amplifier 13 shown in FIG. 5 are used in embodiments of the invention described later.) However, when a logical operation requires that the time of signal arrival be known with certainty, as in the case of the circuit element 14 schematically shown in FIG. 5(D), the circuit, in which the presence of a timing signal T is indispensable, can obviously not be used in an asynchronous system. In other words, if the circuit construction principle of the RSFQ is to be followed, with or without modification, freeing it from the constraints of the synchronous system and moving forward with its application to the asynchronous system requires that a circuit be developed which is capable of arithmetic processing without involving a timing signal, even when the signal representing the two-valued logic is a single-flux-quantum pulse. The present invention was accomplished precisely for this purpose and has as its object to provide an elementary cell useful for constructing asynchronous superconducting logic circuits.